Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAS), complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs).
A well-known phenomenon occurring in electric circuits is the ΔV=IR voltage drop. Whenever a current I flows through a conductor of resistance R, a difference in potential ΔV=IR occurs between the two terminals of the conductor. In ICs, this manifests itself in the fact that the voltage presented at the actual logic gates is not the nominal voltage presented at the SoC—instead, a lower voltage appears, causing a performance degradation (speed reduction).
This is caused by the fact that the power supply circuits are not ideal (they have Rsupply!=0).
Conventionally, external voltage signals are provided to internal die interconnections of integrated circuits such as PLDs, application specific integrated circuits (ASICS), and others, to provide local input power to internal circuitry and integrated circuits. Unfortunately, due to variations in integrated circuit power consumption, IR drops between integrated circuits and external voltage sources can negatively affect local integrated circuit input voltage levels and therefore affect integrated circuit performance. For example, with regard to PLDs, as timing oscillator circuits may be affected by changes to input voltage levels, variations in such input voltage levels to such a timing oscillator circuit may introduce fluctuations in timing clock signal frequency that may lead to incorrect PLD operation.
Others have attempted to resolve IR drop issues by providing a global reference voltage and on-chip global power regulation at some if not all of various integrated circuits localities. However, power regulation often relies on expensive voltage regulators that consume valuable die space. Others have relied on increasing the size and number of power and ground interconnections, and in some cases providing separate power and ground planes. Unfortunately, while increasing the amount and size of the power interconnections or even adding a power and ground plane, may help reduce IR drops, it also requires the use of valuable die space and increases the complexity of the die, especially as die sizes shrink to accommodate the demand for smaller integrated circuits. There is some technology as written in the patent reference 1 to provide power regulation apparatus relatively small, but still there is a need for significant area.
Patent reference 1: U.S. Pat. No. 6,737,925
The solutions to the IR problem discussed so far all rely on the fact that, in a traditional SoC, it is possible to predict with some accuracy the amount of current Icomponent consumed by each component of the SoC (for instance, the CPU, or a video encoder). Using this knowledge, it is possible to size the power supply to each component appropriately: a heavily-used component (for instance, a CPU) will likely be connected to a larger-than-normal power supply (which will have a small R). Other, smaller, components, on the other hand, may only need a smaller power supply (large R) because their current consumption is lower.
This approach, however, is not possible with PLDs. Due to the inherent programmability of PLDs, during the fabrication process it is not possible to predict which regions of the PLD will be heavily used and which ones will be lightly used: such a choice is made by the programming toolchain used to program the device.
As a consequence of this uncertainty, it is common practice to size power supplies for the worst case (heavy utilization) in all regions of the PLD, so as to be able to support any application placement chosen by the programming toolchain.